RF power amplifiers are commonly used in RF circuits as the last active stage in RF transmitters. As a result, an RF power amplifier is typically the largest power consumption device in an RF system; therefore, RF power amplifier systems are designed to be as efficient as possible.
One commonly used technique for improving the efficiency of an RF power amplifier is to feed the DC supply voltage of the RF power amplifier with a DC to DC converter, such that the DC supply voltage is adjusted to allow the RF power amplifier to amplify the RF signals to be amplified properly in an efficient manner. For the DC to DC converter to output the appropriate DC supply voltage, it must be provided with an input signal representative of the desired output voltage or power, which is determined from the magnitude of the RF signals being amplified. By using an RF power detector, the magnitude of the RF signals can be measured.
FIG. 1 shows a typical RF power amplifier system 10 employing a DC to DC converter. The RF output of an RF power amplifier 12 is coupled into an RF power detector 14, which creates a DC voltage representation of the detected RF signal, which is then fed into a decision circuit 16. The decision circuit 16 then creates a control voltage for a DC to DC converter 18 using the signal from the RF power detector 14 and a stable, accurate DC reference voltage, called VREF. The DC to DC converter 18 is powered from a DC supply 20, which may be a battery.
Other power amplifier and DC to DC converter circuits may employ different types of envelope detectors or peak detectors as methods of producing a control voltage based on the power of the incoming RF input signal. However, diode based detectors still suffer from other issues such as delay or difficulty operating with small signal levels using phase modulation, and thus may not be suitable for all applications, as is well known.
FIG. 2 illustrates a two stage power amplifier circuit 22 that overcomes the above discussed shortcomings. The amplifier circuit 22 is the subject of the related U.S. patent application Ser. No. 11/273,739 (hereinafter the “'739 application”). The amplifier circuit 22 internally provides both minimum and maximum operating limits for the DC supply voltage to further improve the efficiency. A maximum operating limit ensures the RF output power from the RF power amplifier 12 does not exceed required levels so that regulatory requirements, such as those imposed by the FCC, thermal limits, and power consumption limits are met. A minimum operating limit ensures that the RF power amplifier 12 has adequate DC supply voltage to operate properly and satisfying linearity requirements of communications standards.
As illustrated in FIG. 2, the DC supply voltage to a final stage 24 is controlled by a DC to DC converter 26. The RF power is detected at the output of a first stage 28. The RF input (RF INPUT) feeds an input matching network 30, which then feeds the first stage 28. The output of the first stage 28 then feeds an interstage matching network 32 and a power detector and decision circuit 34, which detects the RF power from the first stage 28 and generates a DC control voltage, called VSET, for the DC to DC converter 26. The DC to DC converter 26 provides the DC supply voltage, called VCC SUPPLY, to the final stage 24 through a filter inductor 36. The DC to DC converter 26 is powered from a DC supply 38, which may be a battery. The interstage matching network 32 feeds the final stage 24 which drives the RF output through an output matching network 40 to generate the RF output signal (RF OUTPUT).
FIG. 3 illustrates a bipolar power detector and decision circuit disclosed in the '739 application that is one embodiment of the two stage power detector and decision circuit 34 illustrated in FIG. 2. The detector input feeds two attenuator resistors. A first attenuator resistor 42 feeds a common emitter amplifier 44 through a coupling capacitor 46. A second attenuator resistor 48 feeds a common collector amplifier 50. The resistance values of the resistors 42, 48 can be relatively high to minimize loading of the detector circuit 34 input. The resistor values may be greater than 500 ohms.
The common emitter amplifier 44 is comprised of a common emitter amplifier transistor 52 whose collector drives a common emitter amplifier load resistor 54 and a common emitter amplifier filter resistor 56. The common emitter amplifier load resistor 54 is connected to a DC supply voltage, called VBIAS1. The base of the common emitter amplifier transistor 52 is connected to a DC bias voltage, called VBIAS2, through a common emitter amplifier bias resistor 58 thereby creating VIN1 at the base. The common emitter amplifier filter resistor 56 feeds a common emitter amplifier filter capacitor 60, which provides the common emitter amplifier 44 DC output signal, called VOUT1. The common emitter amplifier filter resistor 56 and the common emitter amplifier filter capacitor 60 filter the RF signal to create the DC output signal.
The common collector amplifier 50 is comprised of a common collector amplifier transistor 62 whose emitter drives a common collector amplifier current source 64 and a common collector amplifier filter resistor 66. Voltage VIN2 is provided at the base of the common collector amplifier 62. The collector of the common collector amplifier transistor 62 is connected to a DC supply voltage, called VBIAS3. The common collector amplifier filter resistor 66 feeds a common collector amplifier filter capacitor 68, which provides the common collector amplifier 50 DC output signal, called VOUT2. The common collector amplifier filter resistor 66 and the common collector amplifier filter capacitor 68 filter the detector input signal to create the DC output signal.
VOUT1 and VOUT2 feed the inputs of a differential decision circuit 70, which is comprised of a primary side and a secondary side. VOUT1 feeds the base of a primary side transistor 72 and VOUT2 feeds the base of a secondary side transistor 74. The collector of the primary side transistor 72 drives a primary side load resistor 76 and provides the output from the differential decision circuit 70. The primary side load resistor 76 is connected to a DC supply voltage, called VBIAS4. The emitter of the primary side transistor 72 is connected to a primary side current source 78 and a common emitter resistor 80. The other end of the common emitter resistor 80 is connected to a secondary side current source 82 and the emitter of the secondary side transistor 74. The collector of the secondary side transistor 74 drives a secondary side load resistor 84, which is connected to VBIAS4. The output from the differential decision circuit 70 drives a common collector buffer amplifier comprising a buffer transistor 86 and a buffer current source 88. The emitter of the buffer transistor 86 provides VSET.
FIG. 4 illustrates the response of the power detector and decision circuit 34. If the detector circuit 34 input is less than VIN1, the primary side transistor 72 is active; therefore, VSET will be the value of VMIN. VMIN is determined by the value of VBIAS4 and the voltage drop across the primary side load resistor 76 due to the current being drawn by the primary side current source 78 and the secondary side current source 82 through the common emitter resistor 80.
If the detector 34 input is greater than VIN2, the primary side transistor 72 is off; therefore, VSET will be the value of VMAX. VMAX is determined by the value of VBIAS4, since the voltage drop across the primary side load resistor 76 is virtually zero. The response of the power detector and decision circuit 34 when the detector input is between VIN1 and VIN2 can be adjusted by changing the value of the common emitter resistor 80.
FIG. 5 illustrates an exemplary operational efficiency 90 of the final stage power amplifier 24, which illustrated in FIG. 2 and employs the bipolar power detector and decision circuit 34 of FIG. 3. The operating efficiency is the ratio of RF power to DC power consumption of an amplifier if the gain of the amplifier is large. The power amplifier efficiency (PAE1) curve 92 demonstrates a higher efficiency at higher power output (Pout) levels, but demonstrates a lower efficiency at lower power output levels. The PAE1 at high output power is improved as a result of employing the DC to DC converter 26 producing the DC supply voltage (VCC SUPPLY) controlling the second stage amplifier 24. A quiescent current (ICQ1) 94 of the second stage amplifier 24 is almost constant over the entire power output level range of the final stage power amplifier 24 regardless of VCC SUPPLY or power output level. Notably, the overall power consumption at lower power output levels is mainly attributed to the quiescent current and not amplification. Given the need to reduce power consumption, there is a need to reduce quiescent current when possible without effecting amplifier performance.